Transmission of multi-bit words typically occurs over multi-wire buses. For example, an eight-bit word may be transmitted over a bus having eight wires, one for each bit. But in such conventional busses, each bit carried on a given wire is independent of the remaining bits. As the data rates increase, such conventional communication becomes problematic in that the various bits in a word become skewed from each other as the word propagates over the bus.
Given the issues with skew between multiple bits in high-speed communication, various serializer/deserializer (SERDES) systems have been developed. A SERDES transmitter serializes a multi-bit word into a series of corresponding bits for transmission to a receiver. There can then be no such skew between adjacent bits on a multi-wire bus since a single transmission line (which may be differential) is used in a SERDES system. The SERDES receiver deserializes the received serial bit stream into the original word. However, the SERDES transmission line and the receiver load introduce distortion as the data transmission rate exceeds, for example, 10 GHz. Adjacent bits in the serial bit stream then begin to interfere with each other. Complicated equalizing schemes become necessary to fight the resulting inter-symbol interference and thus it becomes difficult to push SERDES data transmission rates ever higher.
To increase data transmission rates over the SERDES limitations, a three-phase signaling protocol has been developed in which three transmitters drive three separate transmission lines. The following discussion will be directed to the clock generation upon receipt of signals from current-mode transmitters that either source or receive current but voltage-mode transmission may also be used. Since the net current must be zero, all three transmitters cannot be active (either transmitting or receiving current) in a three transmitter system. Similarly, there must be current injected and received so all three transmitters cannot be inactive for any given symbol. So that means that two of the three transmitters will be active for each symbol, with one sourcing current and the other receiving current. From a set of three transmitters, there are three distinct pairs of transmitters that can be active. Within each pair, there are two possibilities depending upon which transmitter is sourcing versus which transmitter is receiving. There are thus six distinct combinations of two active transmitters each sourcing or receiving a given amount of current in a three-transmitter multi-phase system. Each distinct combination of active transmitters may be denoted as a symbol. Since there are six possible symbols, each transmitted symbol represents 2.5 bits. In this fashion, data transmission speeds may be more than doubled over binary transmission at the same symbol rate using a single channel, albeit at the cost of increased power consumption.
In the receiver for a multi-phase communication system, a frontend circuit decodes the received differential currents to produce the corresponding binary symbol. The six different symbols may be represented by six binary words: [100], [010], [001], [110], [101], and [011]. The bits in these symbols may be represented by the binary variables A, B, and C. For example, the symbol [100] corresponds to A=1, B=0, and C=0. To ensure that one of the three binary variables changes state for every transmitted symbol, no self-transition is allowed. For example, suppose the symbol [001] had just been received. The subsequent symbol cannot be [001] as this would violate the ban against self-transition. In this fashion, a clock can be extracted from every received symbol from the guaranteed binary transition of at least one of the binary signals. In practice, however, the extraction of the clock may be complicated by skew between the binary signals that are generated in the receiver frontend circuit responsive to the differential currents on the transmission lines from the transmitter. To generate the clock, each signal A, B, and C may then drive its own pulse generator as shown in FIG. 1A. The frontend circuit that decodes the differential current transmission to produce the binary data signals A, B, and C is not shown for illustration clarity. An A pulse generator receives the A data signal, a B pulse generator receives the B data signal, and a C pulse generator receives the C data signal. Each pulse generator generates a pulse responsive to each rising and falling edge (binary shift or change) in the corresponding data signal.
An OR gate ORs the generated pulses from the pulse generators to produce the clock signal. FIG. 1B illustrates the resulting signal waveforms for ideal behavior (zero skew between the data signals). The pulse generators are configured to generate a pulse at a fifty percent duty cycle with regard to the data word period such that the resulting clock signal has a 50% duty cycle as well. Since there is a guaranteed binary transition of at least one of the A, B, and C signals every data word period, at least one of the pulse generators will generate a pulse accordingly. For example, both signals A and B have a binary transition at the beginning of a data word period B0. Thus, pulse generator A and pulse generator B both generate a pulse in period B0. Similarly, signals A and C both have a binary transition at the beginning of a subsequent data word period B1 so that the pulse generators A and C pulse accordingly. In another data word period B2, only signal B has a binary transition but only one such transition is necessary for the clock signal to continue cycling. The clock (Bit Clk) generated from the ORing of the pulse generator output signals has the desired cycling in each bit period.
But as signal transmission speeds are increased, it becomes more and more difficult to have the zero skew between signals A, B, and C shown in FIG. 1B. FIG. 1C illustrates the more generic case in which signals A, B, and C become jittered and skewed as they propagate through the receiver at high data rates. For example, in a data word period B0, data signal A transitions synchronously with the beginning of the data word period. But data signal B is skewed with regard to the period boundary such that its transition occurs later. As a result, the ORing of the resulting pulses produces a duty cycle of substantially greater than 50% in period B0. Similar distortion and jiitter occurs for the remaining symbol periods as well. The resulting duty cycle distortion and jitter for such a recovered clock produces bit errors when the clock is used to sample the data signals.
Accordingly, there is a need in the art for improved clock generation circuits and techniques for data transmission systems using multi-phase encoding.